This invention relates, in general, to depositing of polysilicon on a semiconductor wafer, and more specifically to selective deposition of polycrystalline silicon, microcrystalline silicon, and amorphous polysilicon.
It has been desired to be able to selectively deposit semiconductor materials on semiconductor wafers, thereby obtaining a self aligning deposition process. This desire has been accentuated as aspect ratios increase and feature size continues to shrink. Aspect ratio is defined as depth divided by width between two adjacent features. By way of example, if the depth between two features such as walls of a trench is held constant and the width or distance between the two features decreases the aspect ratio increases. Standard methods of deposition prove to be insufficient to meet these growing demands. For example, when standard conformal deposition methods are used to fill variable width trenches problems occur depending on the spacing of the trenches. Narrow trenches close and seal long before the wide trenches do. It is therefore necessary to deposit a very thick film in order to fill wide trenches for planarity purposes. Once the deposition is completed and both wide and narrow trenches are filled and sealed an etchback step is required to remove excess material from the surface of the wafer. This leaves material in both wide and narrow trenches yielding a planar surface. This extra processing requires several steps and therefore increases defectivity and cost to a product.
Additionally, it has also been desired to be able to selectively deposit polysilicon or microcrystalline silicon on P/N junction layers to form a part of an active semiconductor device. By way of example is the selective deposition of polysilicon as an emitter of a bipolar transistor.
Recent attempts to obtain selective polysilicon deposition have also had problems. Problems such as loss of selectivity, grain size control, and film contamination are a few problems of major interest.
Loss of selectivity is generally a contamination issue. Contamination causes a loss of selectivity by creating a nucleation site outside of a desired reaction location for growth to occur. Contamination is usually dealt with by rigorous control of all wafer processes and equipment.
Grain size is an important physical parameter of deposition of most films. In the case of selective polysilicon, grain size plays an important part in the future planarity of devices yet to be built. If grain size is large, surface morphology is sharp and angular which requires additional processing steps to planarize the film. These extra processing steps result in additional processing costs as well as higher defectivity. Therefore, there is a need for small grain selective polycrystalline silicon so as to reduce the number of steps to as few as possible.
Film contamination is of great concern in the manufacturing of semiconductor devices. Contamination in films can cause unknown effects that may be hazardous to devices. Work discussed and done by Furumura et. al. "Selective Growth of Polysilicon", Journal Electrochemical Society 133 (1986) pages 379-383, describes a method of obtaining selective growth of polysilicon. This technique introduces trichloroethylene into a gas mixture containing dichlorosilane and hydrogen during epitaxial silicon growth. The contaminating trichloroethylene interrupts the crystal growth pattern and produces polysilicon. This technology is disadvantageous because carbon contamination is found in the bulk of the deposited film. The addition of carbon into the film causes the polysilicon to be more resistive than a noncontaminated film.
It can be seen that standard conformal methods of deposition have severe limitations. Additionally, it is evident that previously disclosed methods for selective deposition of polysilicon also have disadvantages and problems. Therefore, a method for improving selective deposition of polysilicon would be highly desirable.